Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device

ABSTRACT

Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to method and structure formanufacturing a flash memory device. The present invention furtherrelates to the method and structure for manufacturing a flash memorydevice with enhanced gate coupling ratio (GCR) and thereafter a smallerapplied control gate voltage needed in the operation of the flash memorydevice.

2. Description of the Prior Art

Nonvolatile flash memory devices such as erasable programmable read-onlymemory (EPROM) or electrically erasable programmable read-only memory(EEPROM) or flash memory have been widely used and accepted as datastorage devices due to their capabilities to store data after the poweris turned off.

Generally, a flash memory device is very similar to a metal oxidesemiconductor field effect transistor (MOSFET) except that it has astacked gate structure. Two gates are provided generally in a stackedmanner in a flash memory device, one of which is a floating gate,normally formed by polysilicon for the storage of electrical charges,and the other of which is the control gate to control the access ofinformation. The floating gate is generally located underneath thecontrol gate with a dielectric layer (for example, oxide/nitride/oxidestacked structure) lying between the two gates. The floating gate isnamed because it is always in the “floating” state without a connectionto the exterior circuitry. Instead, the control gate is usuallyconnected to a word line. A gate oxide (sometimes called tunnel oxide)lies between the floating gate and the semiconductor substrate.Additionally, source and drain regions are arranged on the semiconductorsubstrate on both sides of the gates.

The operation of a flash memory device will be described briefly asfollows. During a write operation, a high programming voltage is appliedon the control gate, and this forces an inversion region to form in thep-type substrate. The drain voltage is increased to half of the controlgate voltage while the source is grounded, and this increases thevoltage drop between the drain and the source. In the presence of theinversion region, the current between the drain and the sourceincreases. The resulting high electron flow from the source to the drainincreases the kinetic energy of the electrons. This causes electrons togain enough energy to overcome the silicon/silicon oxide energy barrierand be collected in the floating gate. The floating gate can be erasedby grounding the control gate and raising the source voltage to asufficiently high positive voltage to transfer electrons out of thefloating gate to the source gate by tunneling through the thin gateoxide layer.

It is the general trend in the semiconductor market to manufacturedevices with miniaturized dimensions, lower operation voltage, lowercost, higher speed, etc. One of the key features of a flash memorydevice is the gate coupling ratio (GCR) between the floating gate andthe control gate, which affects both the operating voltage and devicespeed. The read/write method of a flash memory is effected by means ofelectrons transferring between the floating gate and the source/draingate.

The gate coupling ratio is defined as the ratio of an induced voltage onthe floating gate to the incident voltage applied on the control gate.For the perfect coupling, this ratio is equal to 100%. Generally,increasing the gate coupling ratio can lower the operating voltage andincrease the device speed at the same time. A few approaches, which havebeen taken to increase the gate coupling ratio, include: increasing theoverlapped area between the floating gate and the control gate; reducingthe dielectric thickness between the floating gate and the control gate;and increasing the dielectric constant (k) of the dielectric layerbetween the floating gate and the control gate.

FIGS. 1A through 1H are schematic cross-sectional views showing theprogression of steps for forming a flash memory device according to aprior art. As shown in FIG. 1A, a semiconductor substrate 110 isprovided, the semiconductor substrate has a plurality of shallow trenchisolation (STI) structures (not shown) therein. A gate oxide layer 111,a first polysilicon (poly 1) layer 112 and a silicon nitride (SiN) layer113 are sequentially formed over the substrate 110. The poly 1 layer 112used as floating gate material is usually grown, for example, bychemical vapor deposition. The silicon nitride layer 113, used as anetching mask for the poly 1 layer etching, is usually also grown bychemical vapor deposition.

As shown in FIG. 11B, a photo resist layer 114 is then formed over thetop of silicon nitride layer 113 and patterned by a conventionalphotolithography process. The photo resist layer 114 is used as anetching mask for silicon nitride layer 113 etching.

As shown in FIG. 1C, an etching process is therefore performed on thesilicon nitride layer 113. Furthermore, the photo resist is strippedafter the etching reaction is completed.

As shown in FIG. 1D, a silicon nitride spacer layer 115 is thendeposited onto the surface as well as the side wall of the patternedsilicon nitride layer 113. Furthermore, in FIG. 1E, an etching processon the poly 1 layer 112 is performed by using the silicon nitride spacerlayer 115 as a self-aligned etching mask. After the self-alignedetching, the silicon nitride layer 113 and the silicon nitride spacer115 are removed, which is as shown in FIG. 1F.

FIG. 1G shows that an insulating stacked structure 116 is then depositedby using, for example, chemical vapor deposition. The insulating stackedstructure is sometimes called inter-poly dielectric because it is usedas the dielectric between the floating gate (poly 1) and the controlgate (poly 2).

FIG. 1H shows that a second polysilicon (poly 2) layer 117 is thendeposited and patterned. The poly 2 layer forms the control gate of theflash memory device. After the poly 2 layer etching, drain and sourceformation (not shown) is therefore conducted by conventional ionimplantation process.

In the prior art, the floating gate surface area is the floating gateperiphery length times the floating gate width “Lw”. As shown in FIG.1I, the floating gate is drawn in a three-dimensional illustration inorder to clearly show how the floating gate surface area is calculated.The floating gate height 312 is typically of thickness 800 Angstroms(A). The floating gate length 314 is typically 2500A. The floating gatewidth 313 herein is designated as “Lw”. Therefore, the floating gatesurface area that is effectively coupled to the control gate is the sumof area 311, area 315 and area 316. Therefore,Floating gate surface area (for the prior art)=(800+2500+800)×Lw=4100Lw

In the prior art as described above, the surface area of the floatinggate overlapped with that of the control gate is limited, which resultsin a gate coupling ratio of only 60%. It would therefore be desirable toprovide a manufacturing method for a flash memory device with a largersurface area of the floating gate overlapped with that of the controlgate so that a higher gate coupling ratio can be obtained.

SUMMARY OF THE INVENTION

In accordance with the present invention, method and structure areprovided for forming a flash memory device with a semiconductor spacerthat substantially increases the overlapped area between the floatinggate and the control gate, which in turn results in a substantiallyimproved gate coupling ratio (GCR).

In one preferred embodiment of the present invention, method andstructure to improve the gate coupling ratio (GCR) for fabricating aflash memory device are provided. The method and structure include thefollowing steps. A gate oxide layer, a first semiconductor layer, and aninsulating layer are formed sequentially over a provided semiconductorsubstrate. Then the insulating layer is partially removed until thepartial first semiconductor layer is exposed. After that, asemiconductor spacer is formed on both the exposed insulating layer andfirst semiconductor layer. The semiconductor spacer is partially removeduntil the insulating layer is exposed. Then the insulating layer ispartially removed in order to expose the first semiconductor layer;thus, the semiconductor spacer protrudes through the surface of thefirst semiconductor layer. Later an insulating stacked structure isformed over the surface of the first semiconductor layer and thesemiconductor spacer. Finally a second semiconductor layer is formedover the insulating stacked structure. Further objectives and advantagesof the present invention will become apparent from a careful reading ofthe detailed description provided herein below with appropriatereference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated and be better understoodby reference to the following detailed description, when taken inconjunction with the accompanying drawings, wherein:

FIGS. 1A through 1H show the schematic cross-sectional views of theprogression of steps for forming a flash memory device in the prior art.

FIG. 1I is a three-dimensional illustration showing the floating gatesurface area in the prior art.

FIGS. 2A through 2I show the schematic cross-sectional views of theprogression of steps for forming a flash memory device in the currentinvention.

FIG. 2J is a three-dimensional illustration showing the floating gatesurface area in the current invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will be made in detail to the present preferred embodiments ofthe invention, examples of which are illustrated in the accompanyingdrawings.

FIGS. 2A through 2I are schematic cross-sectional views showing theprogression of steps for forming a flash memory device according to apreferred embodiment of the current invention. As shown in FIG. 2A, asemiconductor substrate 210, typically a silicon substrate, is provided,and the semiconductor substrate has a plurality of shallow trenchisolation (STI) structures (not shown) therein. A gate oxide layer 211(sometimes called tunnel oxide), a first semiconductor layer 212,typically a polysilicon layer, and an insulating layer 213, typically asilicon nitride layer, are sequentially formed over the semiconductorsubstrate 210. The first semiconductor layer 212, used as floating gatematerial, is usually grown by chemical vapor deposition. The insulatinglayer 213, used as an etching mask for the first semiconductor layeretching, is usually grown by chemical vapor deposition.

As shown in FIG. 2B, a photo resist layer 220 is then formed over theinsulating layer 213 and patterned by a conventional photolithographyprocess.

An etching process is then performed on the insulating layer 213. Next,the photo resist layer 220 is stripped after the etching reaction iscompleted, as shown in FIG. 2C.

As shown in FIG. 2D, a partial etching action is then performed on thefirst semiconductor layer 212 by using the patterned insulating layer213 as an etching mask. Next, in FIG. 2E, a semiconductor spacer 214,for example, a polysilicon spacer, is deposited onto the wholesemiconductor substrate surface. Be one choice, the first semiconductorlayer 212 is etched entirely until partial gate oxide layer 211 isexposed. Then a semiconductor spacer 214 is deposited over the exposedgate oxide layer 211, the first semiconductor layer 212, and theinsulating layer 213. Another choice is to deposit a semiconductorspacer 214 directly over the exposed first semiconductor layer 212 andthe insulating layer 213 without etching the first semiconductor layer212. The semiconductor spacer 214 is used to increase the surface areaof the floating gate overlapped with that of the control gate in orderto increase the gate coupling ratio (GCR) of a flash memory device. Thefirst semiconductor layer 212 and the semiconductor spacer 214 togetherform the new floating gate of the current invention and will bedesignated as layer 230 hereafter.

FIG. 2F shows that a further etching process is performed to etch awaythe top portion of the deposited semiconductor spacer 214 in order toexpose the insulating layer 213 lying underneath it. In this etchingprocess, the semiconductor spacer is used as a self-aligned etchingmask; in other words, no additional photo masks and photolithographyprocess are needed. Therefore a simpler manufacturing process and lowermanufacturing cost are expected by using the method in the currentinvention. After the semiconductor spacer etching, the insulating layeris then removed by a conventional etching process, as shown in FIG. 2G.

FIG. 2H then shows that an insulating stacked structure 215 is depositedby using, for example, chemical vapor deposition.

FIG. 2I shows that a second semiconductor layer 216 is then deposited.The second semiconductor layer forms the control gate of the device.After the second semiconductor layer etching, drain and source formation(not shown) are therefore accomplished by a conventional ionimplantation process.

FIG. 2J shows the new surface area of the floating gate in the currentinvention by a three-dimensional illustration. The new floating gatelength is the sum of the length 317, which is typically 1500 A in thecurrent invention, length 318, and length 319. Lengths 318 and 319 arethe semiconductor spacer bottom lengths, typically 500 A each in thecurrent invention. However, the total floating gate length, which isstill 2500 A, is not increased in the current invention as compared tothat in the prior art. This is very important because the same number offlash memory devices can be fabricated on an 8- or 12-inch siliconwafer. But the surface area that is effectively coupled to the controlgate has been increased to more than twice that in the prior art. Thereason will be explained as follows: the new surface area of thefloating gate in the current invention is the sum of twice area 320, oneof which is on the correspondingly opposite side of the area 320 hiddenin this drawing, twice area 321, similarly, one of which is on thecorrespondingly opposite side of the area 321 hidden in this drawing,and one area of 322. The height 323 of the first semiconductor layer istypically 800 A and the semiconductor spacer height protruding abovesurface 322 is about 1500 A. The new floating gate width, which is still“Lw”, is not changed from that in the prior art. Therefore,New floating gate surface area (for the currentinvention)=2×area320+2×area321+area322

According to this calculation, the new floating gate area that iseffectively coupled to the control gate is as follows,New floating gate surface area (for the current invention)>9100 Lw

It is now quite clear that the capacitance of the inter-poly layer (theinsulating stacked structure) will be increased to more than twice theprior art value since the surface area of the floating gate effectivelycoupled to the control gate has been increased to more than twice theprior art value in the current invention. The GCR therefore is expectedto be increased from 60% in the prior art to more than 75% in thecurrent invention. Once the gate coupling ratio is enhanced, we cantherefore expect a lower voltage to be applied on the control gateduring device operation. A lower applied control gate voltage furtherresults in less hazard of breakdown of the inter-poly dielectric (i.e.,the insulating stacked structure) and hence a better device reliabilityis expected with the current invention.

Although specific embodiments have been illustrated and described, itwill be obvious to those skilled in the art that various modificationsmay be made without departing from what is intended to be limited solelyby the appended claims.

1. A method for manufacturing a flash memory device, said methodcomprising: providing a semiconductor substrate; forming a gate oxidelayer on said semiconductor substrate; forming a first semiconductorlayer on said gate oxide layer; forming an insulating layer on saidfirst semiconductor layer; removing partial said insulating layer untilsaid partial first semiconductor layer is exposed; forming asemiconductor spacer on both said insulating layer and said firstsemiconductor layer; removing partial said semiconductor spacer untilsaid insulating layer is exposed; removing said insulating layer untilsaid first semiconductor layer is exposed, wherein said semiconductorspacer protrudes through the top surface of said first semiconductorlayer; forming an insulating stacked structure on said firstsemiconductor layer and said semiconductor spacer; and forming a secondsemiconductor layer on said insulating stacked structure.
 2. The methodfor manufacturing a flash memory device according to claim 1, furthercomprising removing partial said first semiconductor layer, wherein saidinsulating layer is used as an etching mask.
 3. The method formanufacturing a flash memory device according to claim 2, furthercomprising forming said semiconductor spacer on the side wall of saidfirst semiconductor layer.
 4. The method for manufacturing a flashmemory device according to claim 2, wherein removing partial said firstsemiconductor layer is conducted by an etching process.
 5. The methodfor manufacturing a flash memory device according to claim 1, furthercomprising removing said first semiconductor layer to expose said gateoxide layer, wherein said insulating layer is used as an etching mask.6. The method for manufacturing a flash memory device according to claim5, further comprising forming said semiconductor spacer on said gateoxide layer.
 7. The method for manufacturing a flash memory deviceaccording to claim 1, wherein said semiconductor substrate is of siliconmaterial.
 8. The method for manufacturing a flash memory deviceaccording to claim 1, wherein said semiconductor spacer is ofpolysilicon material.
 9. The method for manufacturing a flash memorydevice according to claim 1, wherein said first semiconductor layer isof polysilicon material.
 10. The method for manufacturing a flash memorydevice according to claim 1, wherein said second semiconductor layer isof polysilicon material.
 11. The method for manufacturing a flash memorydevice according to claim 1, wherein said insulating layer is of siliconnitride material.
 12. The method for manufacturing a flash memory deviceaccording to claim 1, wherein said first semiconductor layer and saidsemiconductor spacer together form a floating gate.
 13. The method formanufacturing a flash memory device according to claim 1, wherein saidsecond semiconductor layer forms a control gate.
 14. The method formanufacturing a flash memory device according to claim 1, wherein saidgate oxide layer is of silicon dioxide (SiO₂) material.
 15. The methodfor manufacturing a flash memory device according to claim 1, whereinsaid insulating stacked structure is of oxide-nitride-oxide stackedstructure.
 16. The method for manufacturing a flash memory deviceaccording to claim 1, wherein said semiconductor spacer can be used asan etching mask in a self-aligned etching process.
 17. The method formanufacturing a flash memory device according to claim 1, wherein saidsteps of removing partial said insulating layer comprises: forming aphoto resist layer on said insulating layer; patterning said photoresist layer; and using said patterned photo resist layer to etch awaypartial said insulating layer.
 18. A flash memory device structure toenhance the gate coupling ratio, said structure comprising: asemiconductor substrate; a gate oxide layer on said semiconductorsubstrate; a first semiconductor layer on said gate oxide layer; asemiconductor spacer protruding through the top surface of said firstsemiconductor layer; an insulating stacked structure over both thesurface of said first semiconductor layer and said semiconductor spacer;and a second semiconductor layer on said insulating stacked structure.19. A flash memory device structure to enhance the gate coupling ratioaccording to claim 18, wherein said semiconductor substrate is ofsilicon material.
 20. A flash memory device structure to enhance thegate coupling ratio according to claim 18, wherein said semiconductorspacer and said first semiconductor layer are configured forconstituting a floating gate.
 21. A flash memory device structure toenhance the gate coupling ratio according to claim 18, wherein saidsecond semiconductor layer is used as a control gate.
 22. A flash memorydevice structure to enhance the gate coupling ratio according to claim18, wherein said insulating stacked structure is an oxide-nitride-oxidestacked structure.